The invention relates to the design and manufacture of integrated circuits, and more particularly, to systems and methods for improving the photolithographic process of manufacturing an integrated circuit.
The electronic design process for an integrated circuit (IC) involves describing the behavioral, architectural, functional, and structural attributes of an IC or electronic system. Design teams often begin with very abstract behavioral models of the intended product and end with a physical description of the numerous structures, devices, and interconnections on an IC chip. Semiconductor foundries use the physical description to create the masks and test programs needed to manufacture the ICs. EDA tools are extensively used by designers throughout the process of designing, verifying, and manufacturing electronic designs.
Photolithography is an optical printing and fabrication process by which features on a photomask are imaged and defined onto a photosensitive layer coating a substrate. The photomask may be used to generate the same master pattern on many locations on a given substrate as well as on many substrates. Photolithography and photomasks are critical to the efficient manufacture of integrated circuits (ICs) and to the progression of the IC industry.
For IC fabrication applications, photomask features correspond to the various base physical IC elements which comprise functional circuit components such as transistors, and interconnect wires, contacts, and vias as well as other elements which are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes.
Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process a large number of material layers of various shapes and thicknesses and with various conductive and insulating properties may be built up to form the overall integrated circuit. The photolithography process generally follows IC design and photomask fabrication.
As represented in FIG. 1, each combination of light/optics has a certain maximum spatial frequency on the wafer. In conventional IC manufacturing processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system. A pitch is a combination of the width of a feature plus the spacing between features. As shown in FIG. 2, a photolithographic process can make a narrow line by adjusting the threshold or dose, but not a smaller pitch.
As the complexity of modern IC designs increase over time, the quantity and density of shapes on an IC design also increase in corresponding fashion. However, the goal of manufacturing IC chips at ever denser and smaller feature sizes is in sharp tension with the pitch limits of existing photolithographic processing tools which are significantly limited by pitch size.
Therefore, it is clearly desirable for integrated circuit designers and manufacturers to have access to improved systems and methods for implementing photolithographic processes which allow of manufacture of features on an integrated circuit with smaller features sizes.